Complementary metal oxide silicon (CMOS) integrated circuits are popular because of their low power consumption characteristics. An ideal CMOS circuit conducts a negligible amount of current when the CMOS circuit is in standby or a quiescent state. Therefore, when a CMOS circuit is not switching states, only a small amount of quiescent current should be conducted by the CMOS circuit. The quiescent current, commonly referred to as Iddq, is composed primarily of leakage current. Iddq is the IEEE symbol for the quiescent power supply current in metal oxide silicon (MOS) circuits. A defective CMOS circuit may draw a significantly larger amount of quiescent current than a non-defective CMOS circuit.
Typically, Iddq testing includes setting a threshold value of Iddq in which the integrated circuit being tested is failed if the Iddq current conducted by the integrated circuit exceeds the threshold value. The Iddq current is measured while inputs to the integrated circuit are driven high or low depending on predetermined states of input test vectors. Iddq testing includes stepping through many different combinations of input test vectors to exercise the functionality within the integrated circuit. The test vectors can be generated by automatic test pattern generation (ATPG) software tools, or by integrated circuit designers.
FIG. 1 shows a standard CMOS gate 10 within an integrated circuit. FIG. 1 also shows the Iddq current conducted by the CMOS gate 10. FIG. 2 shows standard input (Vin) and output (Vout) waveforms of the CMOS gate 10. FIG. 2 also shows the Iddq current conducted by the CMOS gate 10 when there is a defect 21 and when there is not a defect 23.
One of the most difficult elements of Iddq testing is setting the threshold value. An integrated circuit that draws more current than the threshold value of Iddq for any input test vector is declared defective. An integrated circuit that draws less current than the threshold value of Iddq is considered good. If the threshold value is set too high, then integrated circuits that contain defects may be considered good. This decreases the quality level of the integrated circuits considered good. If the threshold value is set too low, then integrated circuits that are free of defects may fail the Iddq test. This increases the cost of the integrated circuits considered good. Therefore, the determination of the threshold value for Iddq testing involves a trade-off between the quality and the cost of the integrated circuits which pass the Iddq testing.
Process variations of the fabrication of the integrated circuits further complicate the determination of the Iddq threshold value. Process variations can affect the current drawn by the integrated circuits. Therefore, process variations can dictate increasing the threshold value of Iddq of a particular integrated circuit. However, it can be difficult to determine whether an increase in the Iddq current conducted by an integrated circuit is caused by process variations or by an increase in defects.
Gattiker and Maly (A. E. Gattiker and W. Maly, "Current Signatures", Proc. VLSI Test Sy mposium, PP. 112-117, 1996) have proposed a method which eliminates some of the threshold selection problems. Traditionally, testing of an integrated circuit ends as soon as the integrated circuit fails the Iddq test. Gattiker and Maly propose that Iddq values be measured for a complete set of input test vectors. A complete set of input test vectors include enough test vectors to completely exercise the functionality of the circuitry within the integrated circuit being tested. From the measured values of Iddq, a current signature is generated. The current signature includes an ordering of the Iddq measurements from the smallest value to the largest value. Gattiker and Maly claim that the magnitude of the measurements is not as important as the shape of a plot of the current signature. If there are no large jumps in the plot of the current signature, then the integrated circuit is designated as good. If the plot of the current signature include any significant jumps or discontinuities, then the integrated circuit is designated as defective.
The Iddq current signature concepts proposed by Gattiker and Maly represent important findings in Iddq current testing analysis. However, these concepts cannot be practically implemented into present-day integrated circuit manufacturing environments. Testing methods using the Gattiker and Maly Iddq current signature concepts require a complete set of input vector test settings to be applied to the integrated circuit under test and the resultant measured values of Iddq current for each input vector test setting to be analyzed. In an integrated circuit manufacturing environment, testing of the integrated circuits must be extremely fast. Additional testing and analysis steps slow down the speed of producing shippable integrated circuits which increases the cost of the integrated circuits.
It is desirable to have a method of Iddq testing which overcomes the limitations of the present single Iddq current threshold comparison tests. Furthermore, it is desirable that the method of Iddq testing be easily implemented into existing integrated circuit manufacturing environments by not requiring excessive storage and analysis of measured values of Iddq.